1. Field of the Invention
The present invention relates to a digital demodulator for demodulating signal waves modulated by digital signals, and also relates to AFC (Automatic Frequency Control) circuits, clock recovery circuits and bit error estimation circuits respectively used for that digital demodulator.
2. Prior Art
Digitization of communication has been studied and realized in the field of data transfer for communication on wires, such as telephone circuits, microwave communication or optical communication between base stations. Also, digitization of mobile communication for automobile telephones or portable telephones whose development has been delayed so far is studied extensively.
As the well-known method of modulating or demodulating digital signals, there can be mentioned the amplitude modulation for changing the amplitude of carrier waves corresponding to state of each digital signal and the so-called angle modulation for changing its phase or frequency.
In the field of digital mobile communication, generally, the angle modulation method which is not susceptible to amplitude distortion due to the signal transfer route is used.
The angle modulation is now described in brief with respect to the so-called .pi./4 shift quadrature phase shift-keying (.pi./4 shift QPSK) method which is excellent in withstandability to distortion and suitable for the mobile communication.
FIG. 16 is a block diagram showing fundamental construction of the .pi./4 shift QPSK system.
Serial/parallel converter 1 converts a row of binary digital data into 2-bit unit data (X, Y). The unit data is called one symbol used as one cycle of data processing. Differential coding circuit 2 produces a base band signal consisting of I and Q channels to which the information of (X, Y) is given respectively corresponding to the change (difference) in signals. The band of the base band signal is limited by low-pass filters (LPF) 3, 4. Thus, amplitude modulation is carried out by multiplying the in-phase and quadrature phase components of carrier wave .omega..sub.c by the band-limited base band signal respectively, and a modulation wave is then obtained by synthesizing both the products.
In case of the phase modulation by the above .pi./4 shift QPSK system, amplitude values "A", "-A" are assigned respectively to the binary signals "1", "0", and four signal-point data (I, Q) are given for one symbol to perform the quadrature phase shift keying. Namely, as shown by the signal-point arrangement with respect to I, Q in FIG. 17, the phase modulation is performed using the signal-point arrangement of QPSK designated by blackened circles (.circle-solid.) and the corresponding .pi./4 shifted signal-point arrangement designated by normal circles (.largecircle.) alternately at each symbol interval. Accordingly, each phase difference .DELTA..PHI. between the two consecutive symbols always becomes odd times the shift of .pi./4 so that the relation between .DELTA..PHI. and the input unit data (X, Y) can be expressed as shown in FIG. 17(b).
As the method of demodulating a modulation wave, the synchronous detection method and delay detection method are well-known. Theoretically, the synchronous detection method has excellent properties, but is likely to generate disadvantageously high-speed fading. Thus, the delay detection method is more preferred, in particular, in case of digital mobile communication where a sudden phase change often occurs.
In the delay detection method, a new modulation wave is detected based on the previous modulation wave delayed by a delay circuit provided with a predetermined delay time. Therefore, these modulation waves should be modulated by a signal processed by the differential coding as described above. In addition, the regeneration of the carrier wave becomes unnecessary. Accordingly, as compared to the synchronous detection method, the delay detection method can be constructed more simply and more suitable for the mobile communication.
For example, in case of the aforementioned .pi./4 shift QPSK, the phase difference .DELTA..PHI. between any given two consecutive modulation waves is obtained by detecting the new modulation wave based on the phase of the previous modulation wave preceding by one symbol, and is then coded in accordance with the data of FIG. 17(b).
FIG. 18 is a block diagram showing one example of conventional digital demodulator for demodulating the .pi./4 shift QPSK modulation wave utilizing the delay detection method.
As shown in the same drawing, the phase modulation wave is converted into a base band signal consisting of I and Q channels respectively corresponding to a first signal having the same frequency as that of the carrier wave .omega..sub.c and a second signal shifted by .pi./2 from the first signal. Then, these I and Q signals are digitized by analog/digital converter (A/D) 7, 8 through low-pass filters 5, 6, respectively.
Thereafter, the digitized signals I and Q are decoded into X, Y based on the relation of FIG. 17(b) after detecting the difference of the signal-point arrangement to the signal preceding by one symbol, that is, the phase difference .DELTA..PHI. through delay detection circuit 9.
From the delay detection circuit 9, the resultant detection signals are sent to data discrimination portions 11, 12 and clock recovery circuit 13, respectively. The clock recovery circuit 13 determines a timing point as will be described below, and supplies a timing clock signal based on that timing point to the data discrimination portions 11, 12 for each one symbol cycle. The data discrimination portions 11, 12 fix the fundamental data (X, Y) using the detection signal based on the timing clock signal. Thereafter, the fundamental data (X, Y) is demodulated by parallel/serial converter 14 into a row of binary data as before the modulation process.
FIG. 19 shows an eye pattern obtained by overlapping the detection signals derived from the X output terminal of the delay detection circuit 9. Generally, the signal level at point (timing point) 10 on which the eye for fixing the binary signal (X=1 or 0) opens most widely is discriminated as the demodulation data for each symbol.
The most important in the above demodulation process is how to determine the timing point. Namely, the conventional clock recovery circuit determines the timing point to produce a timing clock signal. In that case, the so-called zero-cross detection method is generally known as a method of obtaining such a timing point. According to this method, the detection signal is taken out from one output terminal of the delay detection circuit 9 to detect the zero-cross point, at which the signal level crosses 0 (substantially the middle point between the two binary levels), designated by reference numeral 15 in FIG. 19. Then, the points 10 respectively shifted by 1/2 symbol cycle from the zero-cross point 15 are obtained and sent to the data discrimination portion 11, 12 as the timing point signal.
However, in case of such a clock recovery circuit for detecting the timing point using the zero-cross point as mentioned above, the point crossing 0 is distributed in a relatively wide range as denoted by At in the eye pattern of FIG. 19. Therefore, it is difficult to accurately fix the zero-point. If the timing point is determined as the point shifted by 1/2 symbol from that inaccurate zero-cross point, the points at which the eye would be considered to open most widely shift from the most desired points, thereby causing increase of bit error occurrence. Therefore, in a general way, a plurality of zero-cross points must be read to fix their middle value as the real or accurate zero-cross point. However, such a method of fixing the zero-cross point takes much time.
Such inconvenience of this method becomes more noticeable in such a digitized system for radio communication which will be put into practice soon because this system requires frequent change of communication channels and fixing of the aforementioned timing point for each change of channels.
Japanese Patent Application for Disclosure HEI-3-205940 teaches a method in which such digital radio communication is considered first. Namely, in this method, the signal points I, Q of the base band signal to be obtained by a quasi-synchronous detection of the preceding modulation wave are determined respectively on the I-Q coordinate plane. If these signal points deviate from a predetermined signal point arrangement, synchronous correction is carried out by shifting each phase by changing the delay time of the detection circuit so as to correct these positions into originally estimated positions. For example, if the detected signal point is located at a position designated by X in FIG. 20, the shift length is determined by estimating that the point X should be point P which is the nearest to the point X of those shown in FIG. 20.
However, in such a method, the possibility of wrong correction becomes considerably high for each one symbol detection if the deviation of the detected signal points from the predetermined point arrangement is too large to make the estimation unreasonable. Therefore, it takes much time to complete such synchronous correction.
FIG. 21 is a block diagram in which AFC circuit 27 is added to the digital demodulator for demodulating the .pi./4 shift QPSK modulation wave as shown in FIG. 18. In that device, an intermediate frequency signal is produced by mixing the modulation wave with a reference frequency, and is then input into phase quantization circuit 22 through band-pass filter 20 and limiter 21. Thereafter, the quantized signal from the quantization circuit 22 is used to obtain phase difference based on the signal preceding by one symbol using delay detection circuit 23 having a delay time corresponding to one symbol cycle.
The so-obtained phase difference signal is decoded into digital signals X, Y by decoding circuit 24, and these signals X, Y are then fixed based on a timing clock signal from clock recovery circuit 25. Thus, a demodulation signal is obtained by converting these fixed signals into a series of data by parallel/serial converter 26.
In case of the .pi./4 shift QPSK modulation wave, the resultant phase point after the delay detection should be one of the four circles as shown in FIG. 22(a). However, when frequency drift occurs, the phase point takes either one of positions as designated by X in FIG. 22(b). Thus, the phase shift between the positions of FIGS. 22(a) and 22(b) corresponds to the magnitude of frequency drift for one symbol.
Accordingly, the AFC circuit 27 is generally added to correct such frequency drift in the modulation wave. The degree of phase shift is estimated by counting the output of delay detection circuit 23 using up-down counter 28. Then, the count value is subjected to digital/analog conversion through filter 29. Thereafter, the frequency of VCXO 30 for generating the aforementioned reference frequency is so changed that the position of the phase point can coincide with either one of the circles as shown in FIG. 22.
However, even in such an improved system, it is also possible that the phase point which should correctly take the position of circle A emerges at the position X near the wrong position B as shown in FIG. 23 due to considerably large frequency drift. As a result, the AFC circuit 27 carries out wrong correction judging that the position B is the aimed phase point. Therefore, the possibility of obtaining wrong demodulation data still remains high.
Further, in case of mobile communication, base stations are generally placed in fixed areas respectively, and each mobile station performs communication through these base stations. For example, as shown in FIG. 24, mobile station 35 selects one station in the best circuit state to perform communication from base stations A, B and C located near the mobile station.
In this case, as the means for judging whether or not the communication circuit is in a good state, there is a method of comparing the electric field strength of the wave to be transmitted from each base station or a method of measuring the bit error rate (BER) capable of detecting the circuit state including noises or the like factors as well as the synchronous state of the demodulator. Generally, either one or combination of these two methods is used for that purpose.
As a generally-known method of measuring the bit error rate, there can be mentioned a method as shown in FIG. 25(a) in which a series of data (N bits) for measuring a specific bit error rate are inserted in advance at a predetermined interval in a series of information data formed by digitizing information, such as voice or the like elements, on the transmission side, and the bit error rate (n/N) is calculated by detecting the number of bits (n) wrongly received from the series of data for measuring the bit error rate when the demodulation is performed on the reception side. It is also possible to use a method as shown in FIG. 25(b) in which a parity bit is inserted in each group consisting of a plurality of bits (8 bits in the drawing) as a series of information data so as to estimate the bit error rate by the parity check on the reception side.
However, in such a method of measuring the bit error rate, the series of data or parity bit for measuring the bit error rate must be inserted in the series of information data, thereby degrading the communication efficiency. In the former method, in particular, transmission of a series of information data must be discontinued during transmission of the series of data for measuring the bit error rate.
The present invention was made to solve the problems in the clock recovery circuit, AFC circuit and bit error rate estimation means used in the aforementioned conventional digital demodulator and demodulation circuit.
The first object of the present invention is to provide a clock recovery circuit capable of producing desired demodulation signals and a digital demodulator including the clock recovery circuit.
The second object of the present invention is to provide a bit error rate estimation means which does not require any insertion of a specific series of data other than information data on the transmission side and can suppress the degradation of transmission efficiency to a minimum.
The third object of the present invention is to provide an AFC circuit capable of performing well-directed and suitable correction even in case of considerably large frequency drift.